1. Field of the Invention
This invention relates to computer systems and, more particularly, to methods and apparatus for providing a user programmable product term width expander.
2. History of the Prior Art
Programmable logic arrays (PLAs) are arrays of gates which allow a plurality of input values to be manipulated in accordance with various Boolean functions. Essentially, such an array comprises a first series of input conductors each of which may carry a binary input value and a second series of input conductors each of which may carry the inverse of the binary input value carried by an associated one of the first series of input conductors. These first and second input conductors are selectively joined to a third series of conductors each of which is connected to a plurality of AND gates, one input conductor to each one of the third series of conductors. In a PLA, the output of each AND gate (a product term) is available at the input to each of a plurality of OR gates. Since any one of the input conductors may be selectively joined to each of the third series of conductors, all of the input conductors are available to each of the AND gates in a PLA. By connecting various AND gate outputs (product terms) to various OR gates, a particular Boolean function which is the sum of the products terms produced by the AND gates may be furnished at the output of any OR gate. The Boolean output function provided at the output of each of the OR gates is programmable by a user at the manufacturing stage by programming the connections to be made between the input conductors and the conductors of the third series through the particular devices (EPROM cells, fuses, flash EEPROM cells) used in the PLA.
Because the various Boolean functions provided by a PLA are entirely programmable, the speed of operation is slowed to some extent. This occurs because all of the inputs must be available to all of the AND gates, and all of the AND gate outputs must be available to all of the OR gates. Improvements to overcome this loss of speed gave rise to the programmable array logic (PAL.RTM.) in which inputs to the OR gates which sum the product term outputs of the various AND gates are limited in number and hardwired (and are therefore not programmable). Reducing the programmability increases the speed of the array but reduces the options available and limits the number of inputs to each OR gate to a fixed number. Typically, each OR gate receives input of product terms from eight AND gates.
An improvement to PALs provides hardwired OR gates but varies the number of AND gates hardwired to each OR gate so that a variety of functions having different numbers of product terms are available in the array. This type of product is called a programmable logic device (PLD). A PLD offers more options than do PALs but tends to under utilize devices since the average number of product terms connected to any OR gate output is three in typical applications.
Another enhancement is called product term allocation. Product term allocation allows some of the product terms which are inputs to the OR gates to be programmably switched between adjacent OR gates. This allows the numbers of inputs to any OR gate to be increased by a fixed number of input lines and increases the utilization of devices.
However, as computer designs improve, it has become desirable to increase the number of outputs and hence the number of inputs available to programmable logic arrays. As a larger number of input terminals is used, the size of the array increases dramatically. This occurs because there is a relatively constant ratio between the number of inputs and outputs in an array which provides optimum performance. Consequently, as the block grows larger, both the number of inputs and outputs increases in a relatively constant ratio. On the other hand, in typical applications the number of input signals which produce any product term averages about six; and the average number of product terms for each OR gate is from three to four. The result of an attempt to increase the number of inputs to the array is that the number of inputs available to an AND gate increases, and the array slows down in operation because of its complicated construction.
It would be desirable to be able to increase the number of inputs available to a programmable logic circuit without significantly slowing the operational response of the circuit.